At sufficiently high clock rates, a digital signal essentially becomes an analog signal, due to inherent line capacitance and resistance. Consider the following digital output pin connected to a low pass RC filter circuit:
When U1 drives high, the voltage at the output node will not immediately reach VDD because the capacitor needs to charge up first, which is slow due to the resistor. Similarly, when U1 drives low, the output node will not immediately reach GND. Essentially, digital signals oscillating above the RC low pass filter frequency cut-off get turned into varying analog output voltages.
By switching U1 on and off quickly at the right moments in time, we can essentially produce any analog output voltage between VDD and GND. Determining when to switch U1 on and off at the right time is the goal of the Delta Sigma Modulator DAC.
If we want to play audio, frequencies above 22,050 Hz are too high for the human ear to hear, so we can choose values of R1 and C1 dictated by the following equation for an RC low pass filter:
where fc is the 22,050 Hz cut off frequency. After that, R and C can be chosen to be anything that satisfies RC = 1/(2 * PI * 22050). Generally speaking, R should be made large enough to make any internal output impedance of the digital logic driver negligible and to allow for using a smaller, cheaper value capacitor.